New space processor with memory enhancements double performance on space-qualified 3U SBC from Aitec
Aitech Defense Systems Inc. has created its new SP0-S space-qualified 3U CompactPCI SBC with additional on-board memory, as well as voltage and temperature monitoring resources. This radiation-hardened board now provides 1 GB of DDR2 ECC SDRAM, doubling the previous version’s processing performance and increasing performance. 1 GB of User Flash is standard; adding up to 8 GB of User Flash as a future option that will be qualified and available early in 2017.
And with redundant EEPROM Boot memory doubled to a total of 2 MB, the new SP0-S easily handles additional processes and user data storage to provide critical processing power, speed and functionality. Through the use of Aitech’s proprietary algorithms and OS BSPs, the L1 and L2 caches are enabled on the SP0-S, allowing zero (0) wait-state access to program and data, further increasing performance – in most instances up to eight times.
More thermal and operational oversight has been incorporated into this next-gen SP0-S. Three added rad-tolerant temperature sensors monitor the CPU and the thermal interface at two separate points on the board. A rad-tolerant microcontroller also monitors five critical on-board low voltage/high current power supplies as well as the board’s main power inputs.
The SP0-S still features a low overall power consumption of only 10 W. Its solid functionality, large memory arrays and exceptional operating characteristics in the harsh, remote environment of space make the new SBC ideal for high performance, in-orbit systems for LEO (Low), MEO (Medium) and GEO (Geostationary Earth) Orbits.
The board has been fully tested and characterized at NASA-approved cyclotrons at both UC Davis (proton) and Texas A&M (heavy ion) to over 100 kRad (Si). The SBC is latch-up immune to greater than 65 MeV-cm2/mg for reliable operation in either of the three main orbits, or anywhere in between.
A rad-tolerant NXP SOI MPC8548E PowerQUICC-III 1 GHz processor provides 400 MHz of CCB (Core Complex Bus) and an e500 SoC, which integrates an L1 cache with 32 KB each of on-chip instruction and data, and a 512 KB L2 cache.
Extensive on-board I/O potentially reduces the number of additional peripheral cards needed to implement a fully functional C&DH or other subsystems, simplifying system integration.
Routed to the rear panel connectors, I/O includes two Gigabit Ethernet ports, four asynchronous, high-speed RS422 serial communications ports and up to five general purpose discrete I/O channels.
An industry-standard PMC slot and dual PCI buses provide more on-board functionality and performance. A 1 PPS input port allows time synchronization of multiple compute elements in the platform typically used for GPS time synchronization.
Proven Aitech algorithms automatically handle L1/L2 cache mitigation and SEE/SEU characterization, tracking and logging of on-board resources.